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Integrated circuit device interconnection techniques

机译:集成电路设备互连技术

摘要

The present invention relates to multilevel integrated circuit interconnection techniques. An integrated circuit having a number of electronic components along a semiconductor substrate and a first connection layer having a first number of conductors in selective electrical contact with the components is provided. A first insulative layer is formed on the first connection layer with a first pattern of openings therethrough. A second connection layer is established that has a second number of conductors selectively interconnected to the first conductors through the first pattern of openings. A second insulative layer is formed on the first connection layer with a second pattern of openings therethrough. A third connection layer is formed on the second insulative layer having a third dielectric and a third number of conductors selectively interconnecting the second conductors. The first and second insulative layers are preferably etch selective to a dielectric included in the first, second, and third connection layers; and crossover, crossunder, or local interconnects are formed in a different connection layer than routing interconnects to facilitate higher interconnection density.
机译:本发明涉及多层集成电路互连技术。提供了一种集成电路,该集成电路具有沿着半导体衬底的多个电子部件以及具有与这些部件选择性地电接触的第一数量的导体的第一连接层。在第一连接层上形成具有第一开口图案的第一绝缘层。建立第二连接层,该第二连接层具有第二数量的导体,该第二数量的导体通过第一开口图案选择性地互连到第一导体。在第一连接层上形成具有第二开口图案的第二绝缘层。第三连接层形成在具有第三电介质和选择性地互连第二导体的第三数量的导体的第二绝缘层上。第一绝缘层和第二绝缘层优选对第一,第二和第三连接层中包括的电介质具有选择性地蚀刻;优选地,第一绝缘层和第二绝缘层对第一绝缘层和第二绝缘层具有选择性。与跨接,跨接或局部互连形成在与路由互连不同的连接层中,以促进更高的互连密度。

著录项

  • 公开/公告号US6174803B1

    专利类型

  • 公开/公告日2001-01-16

    原文格式PDF

  • 申请/专利权人 VSLI TECHNOLOGY;

    申请/专利号US19980154050

  • 发明设计人 IAN HARVEY;

    申请日1998-09-16

  • 分类号H01L214/763;H01L235/20;H01L294/00;

  • 国家 US

  • 入库时间 2022-08-22 01:05:42

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