GALOIS FIELD MULTIPLIER AND GALOIS FIELD DIVIDER

摘要

PROBLEM TO BE SOLVED: To provide a Galois field multiplier capable of shortening the operation time without requiring any operation clock.;SOLUTION: This Galois field multiplier comprises a GA resistor 10 for setting the bits GA[0]-GA[x] (x=y-1) of a Galois field of y-bit GA; circuits 11-17 for performing operations of GA×α1-GA×αx (α1-αx are power expressions of the Galois field GA) and outputting the multiplication results; a GB resistor 20 for setting the bits GB[0]-GB[x] of a Galois field of y-bit GB; and logic arithmetic circuits A0-A7 and 21 for performing logic operations of (GA×α0*GB[0])+(GA×α1*GB[1])+(GA×α2*GB[2])+... ...+(GA×αx*GB[x]) (wherein * is an AND mark, and + is an exclusive OR mark) and outputting a Galois field GZ (=GA×GB).;COPYRIGHT: (C)2002,JPO