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METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT, EQUIPMENT FOR TESTING SEMICONDUCTOR, AND SEMICONDUCTOR INTEGRATED CIRCUIT

机译:用于测试半导体集成电路的方法,用于测试半导体的设备以及半导体集成电路

摘要

PROBLEM TO BE SOLVED: To shorten the inspection time required for acceleration test at the time of testing a semiconductor integrated circuit including a novolatile memory element.;SOLUTION: The method for testing a semiconductor integrated circuit having a novolatile memory element and a peripheral circuit part other than the novolatile memory element comprises a first step for applying a high voltage to all memory cells in the novolatile memory element and a second step for imparting a test pattern to the peripheral circuit part other than the novolatile memory element while applying a high voltage wherein both steps are performed simultaneously.;COPYRIGHT: (C)2001,JPO
机译:解决的问题:在测试包括易失性存储元件的半导体集成电路时,缩短加速测试所需的检查时间。解决方案:用于测试具有易失性存储元件和外围电路部件的半导体集成电路的方法除了非易失性存储元件之外的其他步骤包括:向该非易失性存储元件中的所有存储单元施加高电压的第一步骤,以及在施加高电压的同时向该非易失性存储元件以外的外围电路部分施加测试图案的第二步骤,其中这两个步骤是同时进行的;版权所有:(C)2001,日本特许厅

著录项

  • 公开/公告号JP2001318126A

    专利类型

  • 公开/公告日2001-11-16

    原文格式PDF

  • 申请/专利权人 MITSUBISHI ELECTRIC CORP;

    申请/专利号JP20000135610

  • 发明设计人 YAMADA TAKASHI;

    申请日2000-05-09

  • 分类号G01R31/30;G01R31/26;G01R31/28;G11C16/02;G11C29/00;

  • 国家 JP

  • 入库时间 2022-08-22 00:55:52

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