COMMON BIAS AND DIFFERENTIAL STRUCTURE BASED DLL WITH FAST LOCKUP CIRCUIT AND CURRENT RANGE CALIBRATION FOR PROCESS VARIATION

摘要

A delay lock loop (DLL) circuit for generating a precisely delayed output signal relative to an input signal. The DLL circuit includes a phase detector for detecting a phase difference between the input signal and the DLL output signal, a lock circuit for detecting when the difference between the input signal and the output signal is zero, and a delay element control circuit for increasing and decreasing the phase of the output signal. This circuit design reduces processing delay, improves jitter performance, and extends the DLL operating frequency range.