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Self-bias and differential structure based PLL with fast lockup circuit and current range calibration for process variation
Self-bias and differential structure based PLL with fast lockup circuit and current range calibration for process variation
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机译:基于自偏置和差分结构的PLL,具有快速锁定电路和电流范围校准功能,可实现工艺变化
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摘要
A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal, which is a selected multiple of an input reference signal. The PLL circuit includes an oscillator control circuit for increasing and decreasing the PLL output frequency signal, a frequency detector for detecting a phase shift between the reference signal and the PLL output signal and produces an error signal, and a fast lock circuit for detecting when the output frequency signal passes the selected multiple of the reference signal. This circuit design provides improved jitter performance, tolerates process variation, and extends the PLL operating frequency range.
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