首页> 外国专利> Integrated semiconductor device with wafer-level burn-in circuit and function decision method of wafer-level burn-in circuit

Integrated semiconductor device with wafer-level burn-in circuit and function decision method of wafer-level burn-in circuit

机译:具有晶圆级预烧电路的集成半导体器件及晶圆级预烧电路的功能判定方法

摘要

An integrated semiconductor device with a wafer-level burn-in circuit includes a test mode register and an access controller. The integrated semiconductor device is set at a voltage force mode by placing the test mode register at a test mode, and is forcedly supplied with prescribed voltages. The wafer-level burn-in is carried out by setting an access controller at a WLBI (wafer-level burn-in) mode with maintaining the test mode. After completing the wafer-level burn-in operation, the WLBI mode is released. Then, an external tester reads test data from a memory core in the test mode, and compares the test data with expected values. The integrated semiconductor device with a wafer-level burn-in circuit can solve a problem of a conventional integrated semiconductor device with a wafer-level burn-in circuit in that it cannot verify the function of the wafer-level burn-in circuit properly.
机译:具有晶片级老化电路的集成半导体器件包括测试模式寄存器和访问控制器。通过将测试模式寄存器设置为测试模式,将集成半导体器件设置为电压强制模式,并强制为其提供规定的电压。通过将访问控制器设置为WLBI(晶圆级预烧)模式并保持测试模式来执行晶圆级预烧。在完成晶片级预烧操作之后,将释放WLBI模式。然后,外部测试仪在测试模式下从存储核心读取测试数据,并将测试数据与预期值进行比较。具有晶片级老化电路的集成半导体器件可以解决传统的具有晶片级老化电路的集成半导体器件的问题,因为它不能正确地验证晶片级老化电路的功能。

著录项

  • 公开/公告号US6437590B1

    专利类型

  • 公开/公告日2002-08-20

    原文格式PDF

  • 申请/专利权人 MITSUBISHI DENKI KABUSHIKI KAISHA;

    申请/专利号US20000649078

  • 发明设计人 TAKASHI TATSUMI;

    申请日2000-08-28

  • 分类号G01R310/20;G01R312/80;H04L12/40;

  • 国家 US

  • 入库时间 2022-08-22 00:49:14

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