A Demonstration of Wafer-Level Layer Transfer of High Performance Devices and Circuits for Three-Dimensional Integrated Circuit Fabrication

摘要

We demonstrate that the wafer-level device stacking protocols we have developed for 3D IC fabrication can preserve the electrical integrity of state-of-the-art silicon devices and ring oscillator circuits. This work presents a new circuit passivation layer that enables layer transfer without any degradation to the back-end copper wiring or low k inter-level dielectrics. We also show high quality wafer bonding by various means using processes suitable for 3D IC fabrication. These techniques are critical for realizing high performance 3D ICs.