Ultra low power voltage translation circuitry and its application in a TTL-to-CMOS buffer

摘要

The power consumed by a voltage translator circuit, such as a TTL-to-CMOS buffer, is substantially reduced by changing the supply voltages provided to the input inverter. By reducing the supply voltage provided to the source of the p-channel transistor of the input inverter, the lowest logic-high TTL voltage applied to the gate turns off the p-channel transistor and turns on the n-channel transistor of the input inverter. By increasing the supply voltage provided to the source of the n-channel transistor of the input inverter, the highest logic-low TTL voltage applied to the gate turns off the n-channel transistor and turns on the p-channel transistor.