Boundary scan cells to improve testability of core-embedded circuits

摘要

As system-on-a-chip (SOC) designs become popular these days, the number of embedded cores in a chip gets larger, raising test issues of glue logic test as well as embedded core test. A core-embedded integrated circuit comprising a first logic block, a second logic block, a signal line coupled between the first logic block and the second logic block for inputting/outputting an input/output signal of the logic blocks, and a boundary scan cell coupled to the signal line for loading /capturing the input/output signal for testing one or both of the first logic block and the second logic block (individually or together), with minimum overhead. Each boundary scan cell includes a data holding capability for data loading from the first and/or second logic block, wherein each boundary scan cell is adapted for serial connection with another of a plurality of like boundary scan cells (boundary scan cell chaining). The boundary scan cells according to the present invention increase testability of the glue logic and the cores with minimal overhead and simple test control, in contrast with a prior art Joint Test Action Group (JTAG) boundary scan design method.