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Damascene process to eliminate copper defects during chemical-mechanical polishing (CMP) for making electrical interconnections on integrated circuits
Damascene process to eliminate copper defects during chemical-mechanical polishing (CMP) for making electrical interconnections on integrated circuits
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机译:镶嵌工艺,用于消除化学机械抛光(CMP)过程中的铜缺陷,以在集成电路上进行电互连
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摘要
A novel copper damascene method for making metal interconnections on semiconductor integrated circuits was achieved. This method avoids overpolishing into a low-k dielectric fluorine-doped glass which would cause copper-flake defects resulting in intralevel electrical shorts. The method utilizes a stacked hard-mask layer on the doped glass layer consisting of a first polish-stop layer, a sacrificial insulating layer and an upper second polish-stop layer. After etching trenches in the stacked hard-mask layer and the doped glass, a copper layer is deposited to fill the trenches and is polished back to the second polish-stop layer. The high polish-back selectivity of the copper to the second polish-stop layer results in improved polish-back uniformity across the substrate. The relatively thin second polish-stop layer can then be polished back and partially into the sacrificial layer without overpolishing and damaging the underlying first polish-stop layer. The sacrificial layer is then removed to complete a level of metal interconnections. The method can be repeated to complete the multilevel of interconnections.
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