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Method and product for improved use of low k dielectric material among integrated circuit interconnect structures
Method and product for improved use of low k dielectric material among integrated circuit interconnect structures
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机译:在集成电路互连结构中改善使用低k介电材料的方法和产品
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摘要
A method is presented for forming a liner upon spaced interconnect structures arranged upon a semiconductor topography. An oxide layer may be deposited to form the liner. The spaced interconnect structures may each include an interlevel dielectric portion arranged upon a metal interconnect portion, with gaps defined between adjacent interconnect structures. A low k dielectric material may be deposited over the interconnect structures such that the low k material substantially fills the gaps between adjacent interconnect structures. The low k dielectric material may then be planarized, preferably by chemical mechanical polishing.
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