首页> 外国专利> Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same

Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same

机译:具有改善的与通孔填充材料的相容性的用于集成电路结构的低介电常数氧化硅基介电层及其制造方法

摘要

An integrated circuit structure is disclosed wherein the capacitance between nearby conductive portions may be lowered using carbon-containing low k silicon oxide dielectric material, without contributing to the problem of via poisoning, by careful control of the carbon content of the dielectric material in two regions of the integrated circuit structure. The first region comprises the region between adjacent raised conductive lines formed over an underlying insulation layer, where undesirable capacitance may be formed horizontally between such adjacent conductive lines, while the second region comprises the region above the raised conductive lines where vias are normally formed extending upward from the raised conductive lines through the dielectric layer to an overlying layer of metal interconnects. In one embodiment, the carbon-containing low k silicon oxide dielectric material used in the first region between adjacent raised conductive lines has a high carbon content to provide maximum reduction of the dielectric constant of the dielectric material for maximum reduction in the horizontal capacitance developed between horizontally adjacent lines, while the carbon-containing low k silicon oxide dielectric material used in the second region above the raised conductive lines has a reduced carbon content to mitigate poisoning of vias formed through the dielectric material in this second region. In another embodiment both the first and second regions have the same or similar reduced carbon content in the carbon-containing low k silicon oxide dielectric material used in both of the respective first and second regions to thereby provide a carbon content sufficient to lower the undesirable capacitance formed horizontally between said adjacent raised conductive lines in said first region, but insufficient to cause via poisoning in vias formed in said second region.
机译:公开了一种集成电路结构,其中可以通过小心地控制两个区域中介电材料的碳含量,使用含碳的低k氧化硅介电材料来降低附近的导电部分之间的电容,而不会导致过孔中毒的问题。集成电路结构。第一区域包括在下面的绝缘层上形成的相邻的凸起的导电线之间的区域,其中在这些相邻的导电线之间可以水平地形成不期望的电容,而第二区域包括凸起的导电线上方的区域,在该区域中通常形成向上延伸的通孔。从凸起的导线穿过电介质层到金属互连的上覆层。在一个实施例中,在相邻的凸起的导线之间的第一区域中使用的含碳的低k氧化硅电介质材料具有高的碳含量,以提供电介质材料的介电常数的最大减小,从而最大程度地减小了之间的水平电容。在水平相邻线之间,而在升高的导线上方的第二区域中使用的含碳低k氧化硅电介质材料具有降低的碳含量,以减轻穿过该第二区域中的电介质材料形成的通孔的中毒。在另一个实施例中,第一区域和第二区域在各自的第一区域和第二区域中使用的含碳低k氧化硅介电材料中具有相同或相似的减少的碳含量,从而提供足以降低不期望电容的碳含量。在所述第一区域中的所述相邻的升高的导线之间水平地形成有电介质,但是不足以引起在所述第二区域中形成的通孔中的通孔中毒。

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