A METHOD TO FORM A HIGH K DIELECTRIC GATE INSULATOR LAYER, A METAL GATE STRUCTURE, AND SELF-ALIGNED CHANNEL REGIONS, POST SOURCE/DRAIN FORMATION

摘要

A process of fabricating a sub-micron MOSFET device, featuring a high dielectric constantgate insulator layer, and a metal gate structure, has been developed. Processes performed attemperatures detrimental to the high dielectric, gate insulator layer, such as formation of spacerson the sides of subsequent gate structures, as well as formation of source/drain regions, areintroduced prior to the formation of the high dielectric, gate insulator layer. This is accomplishedvia use of a dummy gate structure, comprised of silicon nitride, used as a mask to define thesource/drain regions, and used as the structure in which sidewall spacers are formed on. Afterselective removal of the dummy gate structure, creating an opening in an interlevel dielectric layerexposing the MOSFET channel region, deposition of the high dielectric, gate insulator layer, onthe surface of the MOSFET channel region, is performed.