IC test software system for mapping logical functional test data of logic integrated circuits to physical representation

摘要

The present invention relates to a method and apparatus for translating functional test data of a digital logic chip that passes through a simulation model that generally identifies one or more defective nets of a chip to determine the previous ability to determine and display X, It is generally used. The defective nets are processed for the previous type of database to obtain X, Y coordinate data for these nets, which allows them to be the logged data as physical traces on the chip layout. According to an exemplary embodiment, the mapping is performed by taking an output from the functional tester and translating it 126 from a list of failed scan chains 124 to a list of suspicious netlist nodes 129. Then, the X and Y coordinates of the suspicious netlist nodes are identified and stored in the database, which allows the failure analysis and yield increase engineers to explain the failure to give the starting point and the "inline" And provides a starting point for an immediate understanding of the These nodes may then be mutually mapped from the circuit design on the layout of the chip for each of the multiple photomask layers in the design. The detailed failure data is collected and stored at the wafer level as part of a more comprehensive program at the packaged phase, based on what is needed. Therefore, in contrast to obtaining a relatively small amount of low-quality data in a very difficult way, a large amount of high-quality data is obtained in an overall, automated manner.