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Method of forming a inter-metal dielectric layer in a damascene process

机译:在镶嵌工艺中形成金属间介电层的方法

摘要

The invention which is that, due to the high thickness of the prior art metal interlayer insulating film and the degree of integration of devices decrease RC delay in the device operation on the method for forming the damascene (damascene) metal in the process an interlayer insulating film (IMD) of the semiconductor element deepened in order to solve the problems, a silicon oxide film and fluorinated amorphous carbon layer from having a metal interlayer insulating film formed of a laminate structure of (fluorinated amorphous carbon;; aF C), it is possible to have a low dielectric constant without increasing the thickness of the metal interlayer insulating film, fluorinated amorphous by this carbon layer is an etch stop layer serves, more simply, while it at the same time the step screen damascene method for forming a metal interlayer insulation film in the damascene process of a semiconductor device that can improve the integration degree of the device is disclosed.
机译:本发明在于,由于现有技术的金属层间绝缘膜的高厚度和器件的集成度减小了在形成层间绝缘的工艺中形成镶嵌(damascene)金属的方法中的器件操作中的RC延迟。为了解决该问题而加深的半导体元件的膜(IMD)由具有由(氟化非晶碳; aFC)的层叠结构形成的金属层间绝缘膜的氧化硅膜和氟化非晶碳层构成。可能具有较低的介电常数而不增加金属层间绝缘膜的厚度,该碳层的氟化无定形物是蚀刻停止层,更简单地用于同时形成金属中间层的分步丝网镶嵌方法公开了可以改善器件集成度的半导体器件的镶嵌工艺中的绝缘膜。

著录项

  • 公开/公告号KR100356476B1

    专利类型

  • 公开/公告日2002-10-18

    原文格式PDF

  • 申请/专利权人 주식회사 하이닉스반도체;

    申请/专利号KR19990065044

  • 发明设计人 정철모;권혁진;

    申请日1999-12-29

  • 分类号H01L21/316;

  • 国家 KR

  • 入库时间 2022-08-22 00:29:22

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