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Semiconductor memory e.g. DRAM has sub word line driver which charges sub word line to boosting voltage irrespective of activation order between main word line signal and sub word line selection signal
Semiconductor memory e.g. DRAM has sub word line driver which charges sub word line to boosting voltage irrespective of activation order between main word line signal and sub word line selection signal
The sub word line drivers connect the sub word lines to the corresponding main word lines, respectively. Each sub word line driver charges the corresponding sub word line to a boosting voltage, irrespective of an activation order between a sub word line selection signal and a main word line signal. Independent claims are included for the following: (1) Sub word line driver; and (2) Semiconductor memory reliability test method.
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