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The logic circuit verification device, logic circuit verification manner and stores the logic circuit verification program the computer reading possible record media

机译:逻辑电路验证装置,逻辑电路验证方式和存储逻辑电路验证程序的计算机读取可能的记录介质

摘要

PROBLEM TO BE SOLVED: To correctly judge the equivalence of a gated-clock-designed logic circuit at a logic circuit verification device for judging the equivalence of the logic circuit. ;SOLUTION: An equivalence judging circuit generating part 3 generates an equivalence judging circuit for judging the equivalence of a logic at a logic circuit without do-not-care information but generates an equivalence judging circuit for judging the equivalence of a function at a logic circuit with do-not- care information. In a case when the logic circuit is gated-clock-designed, a gated-clock part correcting part 6 corrects the generated equivalence judging circuit to inspect the part. An equivalence judging part 7 judges the equivalence of the logic circuit to inspect based on the corrected equivalence judging circuit.;COPYRIGHT: (C)1999,JPO
机译:要解决的问题:在逻辑电路验证设备上正确判断门控时钟设计的逻辑电路的等效性,以判断逻辑电路的等效性。 ;解决方案:等效判断电路生成部分3生成一个等效判断电路,用于判断没有关心信息的逻辑电路上的逻辑等效性,但是生成一个等效判断电路,用于判断逻辑电路中的功能等效性带有无关信息。在逻辑电路是门控时钟设计的情况下,门控时钟部分校正部分6校正产生的等效判断电路以检查该部分。等效性判断部分7根据校正后的等效性判断电路判断要检查的逻辑电路的等效性。版权所有:(C)1999,JPO

著录项

  • 公开/公告号JP3394888B2

    专利类型

  • 公开/公告日2003-04-07

    原文格式PDF

  • 申请/专利权人 株式会社東芝;

    申请/专利号JP19970153902

  • 发明设计人 北原 健;

    申请日1997-06-11

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 00:20:36

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