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Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein

机译:微电子封装,包括薄膜贴花和其中具有导电通孔的介电粘合剂层

摘要

Microelectronic packages may be fabricated by forming a release layer on a process substrate. A thin film decal is formed on the release layer. The thin film decal includes first and second opposing decal faces, first decal input/output pads on the first decal face, second decal input/output pads on the second decal face and at least one internal wiring layer that electrically connects at least one of the first and second decal input/output pads. The first decal input/output pads are adjacent the release layer and the second decal input/output pads are remote from the release layer. A dielectric adhesive layer is then formed on the second decal face. The dielectric adhesive layer includes first and second opposing dielectric layer faces and conductive vias therein that extend between the first and second opposing dielectric adhesive layer faces. The first dielectric adhesive layer face is adjacent the second decal face and the second adhesive dielectric layer face is remote from the second decal face, such that at least one of the conductive vias electrically connects to at least one of the second decal input/output pads. The dielectric adhesive layer second face is then adhesively bonded to a second level substrate, such as a printed circuit board, that includes second level substrate input/output pads on a face thereof, such that at least one of the conductive vias electrically connects to at least one of the second level substrate input/output pads. The release layer is processed, for example dissolved, to thereby release the process substrate from on the first face of the thin film decal. A first level substrate, such as an integrated circuit chip, is then bonded to the first face of the thin film decal, for example by solder bump reflow.
机译:可以通过在处理基板上形成剥离层来制造微电子封装。在释放层上形成薄膜贴花。薄膜贴花包括第一和第二相对贴花面,在第一贴花面上的第一贴花输入/输出垫,在第二贴花面上的第二贴花输入/输出垫和至少一个内部布线层,该内部布线层电连接至少一个内部贴花层。第一和第二贴花输入/输出垫。第一贴花输入/输出垫邻近释放层,而第二贴花输入/输出垫远离释放层。然后在第二贴花面上形成介电粘合剂层。介电粘合剂层包括相对的第一和第二介电层表面以及在其中相对的介电粘合剂层的第一和第二表面之间延伸的导电通孔。第一介电粘合剂层面与第二贴花面相邻,第二介电粘合剂层面远离第二贴花面,使得至少一个导电通孔电连接至第二贴花输入/输出垫中的至少一个。然后将介电粘合层的第二面粘合到第二层基板,例如印刷电路板,该第二层基板在其表面上包括第二层基板输入/输出焊盘,以使至少一个导电通孔电连接至第二层基板输入/输出垫中的至少一个。对释放层进行处理,例如使其溶解,从而从薄膜贴花的第一面上释放处理基板。然后,例如通过焊料凸点回流,将诸如集成电路芯片之类的第一级衬底结合到薄膜贴花的第一面上。

著录项

  • 公开/公告号US2003038378A1

    专利类型

  • 公开/公告日2003-02-27

    原文格式PDF

  • 申请/专利权人 VIRTUAL INTEGRATION INC.;

    申请/专利号US20010834014

  • 发明设计人 SCOTT L. JACOBS;

    申请日2001-04-12

  • 分类号H01L23/48;H01L23/52;

  • 国家 US

  • 入库时间 2022-08-22 00:10:04

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