Method and apparatus for laying out wires on a semiconductor integrated circuit

摘要

A method for laying out wires in a semiconductor integrated circuit at intervals corresponding to potential differences between nets. A CPU uses a netlist stored in a first file, names and voltages of power supply nets that are stored in a second file, and names and power supply voltages of external input nets stored in a third file to search for nets of equal potentials. The CPU forms groups from nets of equal potentials and obtains the potential at each net. The CPU calculates the potential difference between the nets and sets wire intervals in accordance with the calculated potential differences. The CPU generates wire layout data so that the set intervals are provided.