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Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication
Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication
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机译:牺牲多晶硅侧壁工艺和快速热尖峰退火,用于先进的CMOS制造
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摘要
A process for making abrupt, e.g. 20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. 50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.
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