Method for modeling diffusion of impurities in a semiconductor

摘要

A semiconductor modeling method capable of simulating impurity pileup at a Si/SiO₂ interface, and analyzing electrical characteristics (for example, substrate bias dependency) of a semiconductor, dependent on impurity concentration, under high speed calculation. A portion of impurities in a Si substrate region is caused to migrate to the Si/SiO₂ interface, there by constituting an impurity pileup part. With such a method, it becomes possible to express the impurity pileups at the Si/SiO₂ interface, which could not be expressed with the use of the conventional Fair model, without finding the solution to diffusion equations associated with point defects, that is without the use of the conventional pair diffusion model.