METHOD AND APPARATUS FOR IMPROVING THE TESTING YIELD AND PERFORMANCE OF VERY LARGE SCALE INTEGRATED CIRCUITS

摘要

A method and apparatus to improve the testing of ultra large scale integrated circuits (VLSI) such as synchronous dynamic random access memory (SDRAM) and the test in a more efficient and improve the performance and yield of the product is provided. This method includes to provide a switching circuit for each of the arrays or banks of the device to be selectively tested in separate sequences of test mode signals to the device to identify the limits, interaction, and defects undesirable to the overall performance of the device, obtained in order to correct the test mode signal is a step of the step, and optimize the test method of using the information indicated to improve the design of the device used during the burn-in of production devices. A logic circuit is added to the VLSI device in order to improve the performance test.