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Chip scale package manufacturing method thereof and stack chip scale package using the same
Chip scale package manufacturing method thereof and stack chip scale package using the same
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机译:芯片级封装的制造方法以及使用该方法的堆叠芯片级封装
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摘要
PURPOSE: A chip scale package, manufacturing method thereof and stack chip scale package using the same are provided to enhance productivity by improving a staking structure of the chip scale package. CONSTITUTION: The first solder pad(217a) and the first connection pad(219a,) are formed on the first circuit forming part(210a). A semiconductor chip(201) having a plurality of bonding pads(203) is adhered to the first circuit forming part by adhesive members(220a,220b). The second circuit forming body(210b) includes the second connection pad(219b) and the second solder pad(217b). A plurality of bonding wires(240a,240b) are used for connecting electrically the bonding pads with the connections of the first and the second circuit forming parts. The bonding wires, the bonding pads, and connections pads are sealed with a sealing portion(205). A plurality of solder balls(230) are mounted on the solder pad.
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