INTEGRATED CIRCUIT IN WHICH CHIP LEAKAGE IS REDUCED, AND METHOD FOR REDUCING LEAKAGE

摘要

PROBLEM TO BE SOLVED: To reduce power consumption of an integrated circuit without exerting an influence on the circuit performance.;SOLUTION: The integrated circuit capable of including such an array as static RAM (SRAM) provided with a high threshold array device for reducing leakage and other selected devices is provided. The high threshold device has a thick-formed gate oxide film or a high-k dielectric gate oxide film. The high-threshold device is also used for a non-core circuit like a test circiut. Moreover, an acritical path is discriminated, and an acritical path margin is discriminated. A device threshold higher than specified is selected for an FET of the acritical path based on the acritical path mergin. Delay in the acritical path is re-checked; the FET of the acritical path satisfactory at the re-checking is formed of the thickened gate oxide film, and unselected FETs are formed in normal gate oxide film thickness.;COPYRIGHT: (C)2004,JPO&NCIPI