首页>
外国专利>
Wiring method in layout design of semiconductor integrated circuit, semiconductor integrated circuit and functional macro
Wiring method in layout design of semiconductor integrated circuit, semiconductor integrated circuit and functional macro
展开▼
机译:半导体集成电路布图设计中的布线方法,半导体集成电路及功能宏
展开▼
页面导航
摘要
著录项
相似文献
摘要
In placement of 6-bit interconnection lines in parallel, for example, interconnection lines for three lower-order bits having a high signal change frequency and interconnection lines for three higher-order bits having a low signal change frequency are placed alternately, so that each interconnection line for a lower-order bit is sandwiched by interconnection lines for higher-order bits. With this layout, the interconnection lines for higher-order bits serve like shield lines for the interconnection lines for lower-order bits. This effectively suppresses increase in delay in signal propagation due to change of a signal propagating through an interconnection line for a lower-order bit and a signal propagating through an interconnection line for a higher-order bit to opposite phases, without increasing the area.
展开▼