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Trench DRAM with double-gated transistor and method of manufacturing the same

机译:具有双栅极晶体管的沟槽式DRAM及其制造方法

摘要

A projecting semiconductor layer is formed on a major surface of a semiconductor substrate. A channel region of a first conductivity type is formed in part of the semiconductor layer. Source and drain regions of a second conductivity type are formed in the semiconductor layer such that the source and drain regions sandwich the channel region. A pair of first insulating films are formed on a surface of the channel region. A pair of gate electrodes are formed on a surface of the pair of first insulating films. A trench capacitor is provided near the source region in the semiconductor layer. A second insulating film having a greater thickness than the first insulating films is provided between surfaces of the pair of gate electrodes, which are opposed to the surfaces on which the first insulating films are formed, and a trench capacitor formed adjacent to the trench capacitor.
机译:在半导体衬底的主表面上形成突出的半导体层。在半导体层的一部分中形成第一导电类型的沟道区。在半导体层中形成第二导电类型的源极和漏极区,使得源极和漏极区将沟道区夹在中间。一对第一绝缘膜形成在沟道区的表面上。一对栅电极形成在一对第一绝缘膜的表面上。在半导体层中的源极区域附近设置沟槽电容器。在一对栅电极的与形成有第一绝缘膜的表面相对的表面之间,以及与该沟槽电容器相邻地形成的沟槽电容器之间设有厚度比第一绝缘膜大的第二绝缘膜。

著录项

  • 公开/公告号US2004150037A1

    专利类型

  • 公开/公告日2004-08-05

    原文格式PDF

  • 申请/专利权人 KATSUMATA RYOTA;AOCHI HIDEAKI;

    申请/专利号US20030744818

  • 发明设计人 RYOTA KATSUMATA;HIDEAKI AOCHI;

    申请日2003-12-23

  • 分类号H01L29/76;

  • 国家 US

  • 入库时间 2022-08-21 23:20:22

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