Fixed and variable data-rate, matched-filter receiver

摘要

A matched-filter receiver includes a detector that generates a current signal based on light input thereto. An integrating circuit has an input that is connected to the detector. The integrating circuit integrates the current signal and outputs an integrated signal. A delay circuit is connected to an output of the integrating circuit. The delay circuit delays the integrated signal for a first duration. A comparator circuit includes an inverting input that is connected to the output of the integrating circuit and to an output of the delay circuit. The integrating circuit includes a resistor having a parasitic capacitance. The integrating circuit includes an amplifier circuit that amplifies the integrated signal. The duration that the delay circuit delays the integrated signal can be set to a plurality of duration values. The comparator provides an output signal having one of a first state and a second state. A decision circuit that is connected to the comparator provides a binary decision signal. A clock circuit provides a clock signal having clock edges. The decision circuit includes a flip-flop circuit that is connected to the clock circuit. The flip-flop circuit latches the output of the comparator immediately following at least one of the clock edges.