A High Data-Rate Software Defined Radio Receiver Suited for FPGA Platforms

摘要

Although Alternate Parallel Receiver (APRX) could effectively improve the maximum demodulating rate of the receiver, its frequency domain processing module consumes a large amount of multiplication units when the number of parallel input channels is large, making it unsuitable for use on FPGA software defi ned radio platforms. This paper proposes an optimization scheme by introducing partitioned convolution and exploring the spectrum characteristic of the APRX input data, reducing the usage of multipliers greatly. After the optimization, the number of real multipliers used in the frequency-domain processing module of the 16-ary APRX is reduced from about 576 to 68, with little performance loss. This optimized APRX is fairly suitable for FPGA software defi ned radio platform applications.