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Semiconductor device including interconnects formed by damascene process and manufacturing method thereof

机译:包括通过镶嵌工艺形成的互连的半导体器件及其制造方法

摘要

After etching the interlayer dielectric film 4 formed on the lower layer interconnect line 1 into a shape with holes, the upper layer dielectric film 6 is etched into a shape with trenches utilizing the etching stopper 5. The etching stopper 5 which is exposed at the bottom of the trench is removed by additional etching, and then, the interlayer dielectric film 4 which is exposed at the bottom of the trench is etched back to a predetermined thickness. Subsequently, the hole and the trench are filled with an interconnect metal 10.
机译:将在下层互连线 1 上形成的层间电介质膜 4 蚀刻成带孔的形状之后,对上层电介质膜 6 进行蚀刻。利用蚀刻停止剂 5 制成带有沟槽的形状。通过额外的蚀刻去除暴露在沟槽底部的腐蚀停止层 5 ,然后暴露在沟槽底部的层间介电膜 4 蚀刻回预定厚度。随后,用互连金属 10填充孔和沟槽。

著录项

  • 公开/公告号US2004061233A1

    专利类型

  • 公开/公告日2004-04-01

    原文格式PDF

  • 申请/专利权人 SANYO ELECTRIC CO. LTD.;

    申请/专利号US20030664875

  • 发明设计人 NAOTERU MATSUBARA;KAZUNORI FUJITA;

    申请日2003-09-22

  • 分类号H01L23/48;H01L23/52;H01L29/40;

  • 国家 US

  • 入库时间 2022-08-21 23:16:09

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