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High-speed chip-to-chip communication interface with signal trace routing and phase offset detection
High-speed chip-to-chip communication interface with signal trace routing and phase offset detection
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机译:具有信号走线和相位偏移检测功能的高速芯片间通信接口
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摘要
A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 40-bit wide data every 167 Mhz clock cycle, and the interconnect bus transmits 10-bit wide data at every transition of a 333 Mhz clock cycle. In another embodiment, the transmitter controller accepts 32-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 32-bit wide data every 167 Mhz clock cycle, and the interconnect bus of this embodiment transmits 8-bit wide data at every transition of a 333 Mhz clock cycle. Output pins of the transmitter interface can be connected to any input pins of the receiver interface. Furthermore, the high-speed parallel interface does not require a fixed phase relationship between the receiver's internal clock(s) and the bus clock signal.
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