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Non-reducible, low temperature sinterable dielectric ceramic composition, multilayer ceramic chip capacitor using the composition and method for preparing the multilayer ceramic chip capacitor

机译:不可还原的低温可烧结介电陶瓷组合物,使用该组合物的多层陶瓷片状电容器和制备多层陶瓷片状电容器的方法

摘要

Multilayer ceramic chip capacitors which satisfy X5R (−55 to 85° C., &Dgr;C=±15%) requirements and which are compatible with reducing atmosphere sintering conditions so that base metals such as nickel and nickel alloys may be used for internal electrodes are made in accordance with the invention. ;The multilayer ceramic chip capacitor comprises alternately staked, dielectric ceramic layers and internal electrode layers wherein dielectric ceramic layers comprise per 100 mol of BaTiO3, BaTiO3; MgCO3: 0.2 to 3.0 mol; at least one selected from Y2O3, Ho2O3, Dy2O3 and Yb2O3: 0.05 to 1.5 mol; Cr2O3: 0.1 to 1.5 mol; BaxCa(1−x)SiO3 (provided that 0≦x≦1): 0.2 to 3.0 mol; and Mn2V2O7: 0.01 to 1.5 mol. The multilayer ceramic chip capacitor of the present invention has a high dielectric constant, satisfies X5R characteristics can be sintered at a low temperature of 1,200 to 1,250° C.
机译:满足X5R(≤55至85°C,& C&amp ;;≥15%)要求并且与还原气氛烧结条件兼容的多层陶瓷芯片电容器,因此可以使用诸如镍和镍合金的贱金属内部电极根据本发明制造。 ;多层陶瓷片状电容器包括交替堆放的介电陶瓷层和内部电极层,其中介电陶瓷层每100摩尔包含BaTiO 3 ,BaTiO 3 ; MgCO 3 :0.2至3.0摩尔;至少一个选自Y 2 O 3 ,Ho 2 O 3 ,Dy 2 O 3 和Yb 2 O 3 :0.05到1.5摩尔; Cr 2 O 3 :0.1至1.5摩尔; BaxCa(1 + x)SiO 3 (假设为0lE; x≦ 1):0.2至3.0 mol; Mn 2 V 2 O 7 :0.01至1.5 mol。本发明的多层陶瓷片状电容器具有高介电常数,满足X5R特性,可以在1200至1250℃的低温下烧结。 C。

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