Method for designing a semiconductor integrated circuit which includes consideration of parasitic elements on critical data paths

摘要

In a layout data forming step and a layout outputting step after a netlist is read, layout data is formed based on the netlist. In a path sorting step in parallel with these steps, a delay for each path is calculated based on the netlist to compare with a predetermined delay. Only a path having a delay exceeding the predetermined delay is output as a target path to an extraction path file. Then in a parasitic element extracting step, parasitic elements are extracted only from a graphic pattern included in the target path in the layout data while referencing the extraction path file.