FLASH MEMORY DEVICE WITH INCREASE OF EFFICIENCY DURING AN APDE (AUTOMATIC PROGRAM DISTURB AFTER ERASE) PROCESS

摘要

Source resistance or positive voltage be couple to the source and apply back bias voltage substance or p-well flash cell enhance during programming efficiency and/or an APDE (automatic programmer disturb wipe after process memory devices for a flash. In addition, in the system and method for programming flash memory devices, the programming of the multiple flash memory storage unit arrays of selection of flash memory cells. Control gate program voltage is applied to the selected flash memory cell of control grid, and drill bit bit line program voltage is applied to drain electrode and connects via public bit selected flash memory cell line terminal to the drain electrode of which selected flash memory cell. A kind of system and method, for (automatic programmer to disturb process after erasing, and multiple flash memory cells of a flash memory cell array are chosen so as to be wiped free of correction executing APDE. (automatic programmer disturbs voltage and is applied to public bit line terminal corresponding to selected column flash cell APDE after bit line erasing. (voltage is applied to column flash cell selected by the respective control grid of each flash memory cell to control grid APDE after automatic programmer disturbs erasing. Alternatively, the self-biasing that the control grid of each flash memory cell is coupled in source configures so that control grid APDE voltages are not applied to column flash cell selected by the respective control grid of each flash memory cell.