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Circuit and method of compensating voltage drop of internal power voltage for cell array in semiconductor memory device
Circuit and method of compensating voltage drop of internal power voltage for cell array in semiconductor memory device
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机译:补偿半导体存储器件中的单元阵列的内部电源电压的压降的电路和方法
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摘要
PURPOSE: A circuit for compensating the voltage drop of an inner power voltage for a cell array in a semiconductor memory device and a method for compensating the voltage drop are provided to satisfy the requirement for the low power voltage and the requirement for the high power voltage. CONSTITUTION: A circuit for compensating the voltage drop of an inner power voltage for a cell array in a semiconductor memory device includes a pull-up driver and a pulse width control circuit(420). The pull-up driver pulling up the inner power voltage level for the cell array to an external power voltage level in response to the pulse width. And, the pulse width control circuit(420) controls the pulse width of the pulse signal in response to the level detection signal. The level detection signal is capable of shifting the logic state in response to the sense control signal to control the sensing of the data stored at the memory cell and the external power voltage.
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