首页> 外国专利> METHOD FOR IMPROVING DESIGN RULE OF SEMICONDUCTOR DEVICE TO IMPROVE DESIGN RULE MARGIN OF WELL OF SECOND CONDUCTIVITY TYPE

METHOD FOR IMPROVING DESIGN RULE OF SEMICONDUCTOR DEVICE TO IMPROVE DESIGN RULE MARGIN OF WELL OF SECOND CONDUCTIVITY TYPE

机译:改进半导体器件设计规则以提高第二电导率型井设计规则裕度的方法

摘要

PURPOSE: A method for improving the design rule of a semiconductor device is provided to improve a design rule margin of a well of the second conductivity type by forming a deeper trench in the well of the second conductivity type than in a well of the first conductivity type. CONSTITUTION: The first insulation layer is formed on a substrate(100). A well(102) of the first conductivity type is formed in a predetermined region of the substrate. Source ions including fluorine are implanted into a region adjacent to the well of the first conductivity type to form a well(103) of the second conductivity type. The substrate in the well of the second conductivity type is more deeply etched than the substrate in the well of the first conductivity type so as to form a step of a trench in the isolation region between the wells of the first and second conductivity types.
机译:目的:提供一种用于改善半导体器件的设计规则的方法,以通过在第二导电类型的阱中形成比在第一导电类型的阱中更深的沟槽来提高第二导电类型的阱的设计规则裕度类型。构成:第一绝缘层形成在基板(100)上。在基板的预定区域中形成第一导电类型的阱(102)。将包含氟的源离子注入到与第一导电类型的阱相邻的区域中,以形成第二导电类型的阱(103)。第二导电类型的阱中的衬底比第一导电类型的阱中的衬底被更深地蚀刻,以便在第一导电类型和第二导电类型的阱之间的隔离区域中形成沟槽的台阶。

著录项

  • 公开/公告号KR20040087043A

    专利类型

  • 公开/公告日2004-10-13

    原文格式PDF

  • 申请/专利权人 MAGNACHIP SEMICONDUCTOR LTD.;

    申请/专利号KR20030021282

  • 发明设计人 LEE JIN HYEOK;

    申请日2003-04-04

  • 分类号H01L21/76;

  • 国家 KR

  • 入库时间 2022-08-21 22:47:52

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