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Being the output circuit and comparator null output circuit which

机译:作为输出电路和比较器零输出电路,

摘要

PROBLEM TO BE SOLVED: To surely fix an output voltage to a low level or a high level when a power supply voltage drops below the lower limit voltage of a circuit by applying a divided power supply voltage to the gate of a 2nd transistor and cutting off the 2nd transistor when the power supply voltage is smaller than prescribed due to this. SOLUTION: An input voltage VIN is respectively inputted to the gates of P and N channel transistors Q1 and Q2 being a complementary pair, and inverted outputs from the drains of the Q1 and Q2 are combined to obtain a voltage VOUT to be applied. A depression transistor Q3 is connected to the output. The drain of a P channel transistor Q11 is further connected to the source of the Q1, and the source of the Q11 is connected to a power supply voltage VDD of a high potential side. On the other hand, the source of the Q2 is connected to a power supply voltage VSS of a low potential side. A voltage dividing means of a power supply voltage consisting of resistor R11 and R12 is connected to the gate of the Q11.
机译:解决的问题:通过将分压的电源电压施加到第二晶体管的栅极并切断,以在电源电压下降到电路的下限电压以下时,将输出电压固定为低电平或高电平。因此,第二电源电压小于规定的第二晶体管。解决方案:输入电压VIN分别输入到作为互补对的P和N沟道晶体管Q1和Q2的栅极,并且Q1和Q2的漏极的反相输出被组合以获得要施加的电压VOUT。低压晶体管Q3连接到输出。 P沟道晶体管Q11的漏极进一步连接到Q1的源极,并且Q11的源极连接到高电势侧的电源电压VDD。另一方面,Q2的源极连接至低电势侧的电源电压VSS。由电阻器R11和R12组成的电源电压的分压装置连接到Q11的栅极。

著录项

  • 公开/公告号JP3711773B2

    专利类型

  • 公开/公告日2005-11-02

    原文格式PDF

  • 申请/专利权人 セイコーエプソン株式会社;

    申请/专利号JP19980362583

  • 发明设计人 梅田 博之;

    申请日1998-12-21

  • 分类号H03K17/24;H03K19/0175;

  • 国家 JP

  • 入库时间 2022-08-21 22:28:53

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