Input/output switching arrangement for semiconductor circuits, a method for testing driver circuits in semiconductor circuits

摘要

A test for internal circuits in semiconductor circuits, for example DRAMs, in a reduced-I/O mode requires that contact be made only with a subset of the signal connections on the semiconductor circuit. Driver circuits associated with signal connections which are not contained in the subset are internally connected to a test potential line (TPOT), and the latter is connected to a supply potential (GND, VCC) for the semiconductor circuit or to a monitor connection (MON), so that all driver circuits can be tested or monitored under load even during a burn-in in the reduced-I/O mode. During the testing of semiconductor circuits in the reduced-I/O mode, the test coverage is increased.