A / output switching arrangement for semiconductor circuits and method for testing of driver circuits, of semiconductor circuits

摘要

A testing of internal circuits (9) of semiconductor circuits (4), such as drams, requires in a reduced - i / o - mode, the contacting only a subset of the signal connections (1) of the integrated circuit (4). Driver circuits (2), which are not contained in the partial quantity signal terminals (1) are allocated, internally to a test potential line (potential tpot) and the latter is connected to a supply potential (gnd, vcc) of the integrated circuit (4) or with a monitor connection (mon), so that even during a burn - into the in the reduced - i / o - mode all of the driver circuits (2) under load, tested, and / or can be monitored. In the testing of semiconductor circuits (4) in the reduced - i / o - mode, the test coverage of increased.