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Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology
Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology
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机译:采用低介电常数材料的密封垫片,可减少CMOS技术中栅极和漏极之间的寄生电容
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摘要
The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced switching speeds. More particularly, a sidewall spacer formed upon a semiconductor substrate adjacent a conductive gate structure includes a material having a low dielectric constant (low-k) to mitigate parasitic capacitance between the gate structure, the sidewall spacer and a conductive drain formed within the semiconductor substrate. The low-k sidewall spacer is encapsulated within a nitride material which is selective to etchants such that the spacer is not altered during subsequent processing. The spacer thus retains its shape and remains effective to guide dopants into desired locations within the substrate.
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