Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer

摘要

The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 Å to about 800 Å having a dielectric constant of less than about 3.2, depositing a silicon oxide inter- dielectric layer, and forming the local interconnect through the inter- dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.