METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A C-V MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND A DEVICE THEREBY FORMED

摘要

A method of determining the active region width (10) of an active region (4) by measuring the respective capacitance values (C₁₀₀, C_100′, C_100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element(16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (W_i) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective capacitance values (C₁₀₀, C_100′, C_100″) as a quasi-linear function (CW) of the respective predetermined widths (W_i), extrapolating a calibration term (W_C=0) from the quasi-linear function (CW), and subtracting the calibration term (W_C=0) from the respective predetermined widths (W_i) to define and constrain the active region width (10) for facilitating device fabrication.