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Apparatus and methods for determining and localization of failures in test structures using voltage contrast

机译:使用电压对比确定和定位测试结构中的故障的设备和方法

摘要

Disclosed is test structure that can be fabricated with minimal photolithography masking steps and in which defects may be localized to specific layers. Mechanisms for fabricating such test structures are also provided. In one embodiment, a semiconductor test structure suitable for a voltage contrast inspection is provided. The test structure includes one or more test layers corresponding to one or more product layers selected from a plurality of product layers of an integrated circuit (IC) product structure. The number of the selected one or more test layers is less than a total number of the plurality of product layers of the product structure, and the test layers include at least a first portion that is designed to have a first potential during the voltage contrast inspection and a second portion that is designed to have a second potential during the voltage contrast inspection. The first potential differs from the second potential. The selected one or more test layers which correspond to product layers are selected from the plurality of product layers such that defects found in the test layers of the test structure during the voltage contrast inspection represent a prediction of defects in the corresponding product structure.
机译:公开了可以用最少的光刻掩模步骤来制造的测试结构,并且其中缺陷可以定位在特定的层上。还提供了用于制造这种测试结构的机构。在一个实施例中,提供了一种适合于电压对比检查的半导体测试结构。该测试结构包括与从集成电路(IC)产品结构的多个产品层中选择的一个或多个产品层相对应的一个或多个测试层。所选的一个或多个测试层的数量小于产品结构的多个产品层的总数,并且测试层至少包括第一部分,该第一部分被设计为在电压对比检查期间具有第一电势第二部分被设计成在电压对比检查期间具有第二电势。第一电位不同于第二电位。从多个产品层中选择与产品层相对应的一个或多个测试层,以使得在电压对比检查期间在测试结构的测试层中发现的缺陷表示对相应产品结构中的缺陷的预测。

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