An integrated chip scale package (CSP) (55) arranged in a vertical stack and comprising two or more single chip package subassemblies having an upper level CSP subassembly (20) superimposed directly above a lower level CSP subassembly (50). The lower-most CSP subassembly (50) in the vertical stack contains an array of solder balls (64) for interconnection to a printed wiring board. The vertical electrical connection (60) between the upper and lower level package subassemblies (20, 50) is accomplished by using wire bonding from perimeter wire bonding pads (40) located on an upper level substrate extension to matching perimeter wire bonding pads (40-1) located on a lower level substrate extension (24) that is longer in length than the upper level substrate extension. The stacked subassemblies (20, 50) are bonded together by using a thin adhesive material, and the perimeter wire bonds are encapsulated by an encapsulant (62) for protection. The assembled vertical stack has the appearance of a single CSP but is shorter in height than two individual packages that are stacked together with solder ball interconnects located therebetween.
展开▼
