首页> 外国专利> METHOD OF FORMING BIT LINE CONTACT OF SEMICONDUCTOR DEVICE FOR PREVENTING BRIDGE PHENOMENON DUE TO INCREASE OF TOP AREA OF BIT LINE CONTACT

METHOD OF FORMING BIT LINE CONTACT OF SEMICONDUCTOR DEVICE FOR PREVENTING BRIDGE PHENOMENON DUE TO INCREASE OF TOP AREA OF BIT LINE CONTACT

机译:由于位线接触面积增加而形成防止桥现象的半导体装置的位线接触方法

摘要

Purpose: a kind of method for the dotted line contact being used to form semiconductor device is arranged to prevent a bridge phenomenon, due to the increase of a top area of bit line contact, passes through a bottom section of fixed bit line contact. Construction: a first insulating layer (11) is formed in semi-conductive substrate (10). Second insulating layer (14) is formed in first insulating layer. One dotted line contacts, and for making a part exposure of landing plug (13), is formed by selectively etching the first and second insulating layers. One wet cleaning process is performed to remove remaining insulating materials from a bottom face of bit line contact.
机译:目的:布置一种用于形成半导体器件的虚线接触的方法,以防止由于位线接触的顶部面积的增加而穿过固定位线接触的底部的桥接现象。结构:在半导体衬底(10)中形成第一绝缘层(11)。在第一绝缘层中形成第二绝缘层(14)。通过选择性地蚀刻第一绝缘层和第二绝缘层,形成一个虚线接触,并用于使接地插塞(13)部分暴露。进行一种湿法清洁工艺以从位线接触的底面去除残留的绝缘材料。

著录项

  • 公开/公告号KR20050008317A

    专利类型

  • 公开/公告日2005-01-21

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20030048231

  • 发明设计人 JUNG WOO DUCK;

    申请日2003-07-15

  • 分类号H01L21/28;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:58

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