首页> 外国专利> Method for forming bit line contacts and bit lines during the formation of a semiconductor device, and devices and systems including the bit lines and bit line contacts

Method for forming bit line contacts and bit lines during the formation of a semiconductor device, and devices and systems including the bit lines and bit line contacts

机译:在半导体器件的形成过程中形成位线触点和位线的方法,以及包括位线和位线触点的器件和系统

摘要

A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases processing latitude, particularly the spacing between the bit lines which, with conventional processes, may strain photolithographic limits. A semiconductor device formed using the method, and an electronic system comprising the semiconductor device, are also described.
机译:一种形成半导体器件的方法,包括以不同的水平形成第一和第二位线。在不同水平上形成位线增加了处理范围,特别是位线之间的间隔,这在常规工艺中可能使光刻极限受限。还描述了使用该方法形成的半导体器件以及包括该半导体器件的电子系统。

著录项

  • 公开/公告号US2007241378A1

    专利类型

  • 公开/公告日2007-10-18

    原文格式PDF

  • 申请/专利权人 SEIICHI ARITOME;

    申请/专利号US20060404209

  • 发明设计人 SEIICHI ARITOME;

    申请日2006-04-13

  • 分类号H01L29/94;

  • 国家 US

  • 入库时间 2022-08-21 21:06:59

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