首页> 外国专利> SEMICONDUCTOR MEMORY DEVICE AND FABRICATING METHOD THEREOF TO PREVENT REDUCTION OF LENGTH OF EFFECTIVE GATE DUE TO DIFFUSION OF IMPURITIES

SEMICONDUCTOR MEMORY DEVICE AND FABRICATING METHOD THEREOF TO PREVENT REDUCTION OF LENGTH OF EFFECTIVE GATE DUE TO DIFFUSION OF IMPURITIES

机译:防止由于杂质扩散而降低有效门的长度的半导体存储器及其制造方法

摘要

PURPOSE: A semiconductor memory device and a fabricating method thereof are provided to prevent reduction of a length of an effective gate due to diffusion of impurities by insulating an impurity region and a gate electrode without forming a LOCOS region. CONSTITUTION: A semiconductor substrate(1) has a main surface. First and second impurity regions are respectively formed on the main surface of the semiconductor substrate. First and second insulating layers are formed on the first and second impurity regions, respectively, and deposited on the main surface so as to protrude above the main surface. An ONO(Oxide-Nitride-Oxide) layer(2,3,4) is formed between the first and second insulating layers. A gate electrode extends over the ONO layer and the first and second insulating layers.
机译:目的:提供一种半导体存储器件及其制造方法,以通过在不形成LOCOS区域的情况下使杂质区域和栅电极绝缘来防止由于杂质的扩散而导致的有效栅极的长度的减小。构成:半导体衬底(1)具有一个主表面。第一和第二杂质区分别形成在半导体衬底的主表面上。第一绝缘层和第二绝缘层分别形成在第一杂质区域和第二杂质区域上,并且沉积在主表面上,以突出到主表面上方。在第一绝缘层和第二绝缘层之间形成ONO(氧化物-氮化物-氧化物)层(2、3、4)。栅电极在ONO层以及第一绝缘层和第二绝缘层上延伸。

著录项

  • 公开/公告号KR20050016123A

    专利类型

  • 公开/公告日2005-02-21

    原文格式PDF

  • 申请/专利权人 RENESAS TECHNOLOGY CORP.;

    申请/专利号KR20040061284

  • 发明设计人 TSUJI NAOKI;

    申请日2004-08-04

  • 分类号H01L21/8229;H01L27/115;

  • 国家 KR

  • 入库时间 2022-08-21 22:05:53

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