首页> 外国专利> THE FABRICATION METHEOD OF LOW VOLTAGE BULK TYPE VARISTOR BY CONTROLING THE BOUNDARY NUMBER BETWEEN ELECTRODES

THE FABRICATION METHEOD OF LOW VOLTAGE BULK TYPE VARISTOR BY CONTROLING THE BOUNDARY NUMBER BETWEEN ELECTRODES

机译:通过控制电极间的界数来制造低压灯泡形压敏电阻的方法

摘要

The varistor, which protects the elements of the circuit from surge voltages in electronic products is published.; Between the varistor element of the present invention stacked chip varistor element and unlike bulk type varistor to the use of grain boundaries existing on the surface of the device by using a device such as a screen printer to the varistor surface and applying the electrode material according to a pattern, and electrode material controlling the number of grain boundaries present in the can to have a low-voltage characteristics and safety with respect to surge voltage, such as a chip varistor, it is possible to compact produced according to the grain structure of the varistor.
机译:出版了用于保护电路元件免受电子产品浪涌电压影响的压敏电阻。在本发明的压敏电阻元件和叠置型压敏电阻元件之间,与块状压敏电阻之间的区别在于,通过使用诸如丝网印刷机之类的装置将压敏电阻表面上存在的装置用于电极表面,并使用根据图案,以及控制罐中存在的晶界数量以具有低电压特性和相对于浪涌电压的安全性的电极材料(例如片状压敏电阻),可以根据其晶粒结构进行紧凑生产压敏电阻。

著录项

  • 公开/公告号KR20050080956A

    专利类型

  • 公开/公告日2005-08-18

    原文格式PDF

  • 申请/专利权人 KIM YEONG CHEOL;

    申请/专利号KR20040009149

  • 发明设计人 JUNG JU YONG;KIM YEONG CHEOL;

    申请日2004-02-11

  • 分类号H01C7/10;

  • 国家 KR

  • 入库时间 2022-08-21 22:04:45

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