Plausibility testing circuit for testing for the correct operation of an analogue to digital converter in a safety-relevant application, by comparison of ADC inputs and outputs with reference signals

摘要

Plausibility testing circuit comprises an ADC that generates an output digital signal from an analogue input (ADC1) and a control unit (11) that generates a reference signal (VREF) from the analogue input signal. A comparator (19) is used to compare analogue input and reference signals, while an evaluation unit (13) is used to compare the digital signal to the comparison signal (VMON). If the evaluation unit generates a difference signal that exceeds a preset threshold, an error signal (VERR) is output. An independent claim is made for a plausibility testing method for testing for the correct operation of an analogue to digital converter in a safety-relevant application.