Memory system, e.g. DRAM, performs data transmission between control device and memory devices via two internal data busses, and only via first data bus for further internal data packets

摘要

The memory system is designed, so that for a number of internal data packets (iBurst), the data transmission per iBurst between a control device (CTRL) and memory devices (MEM1, MEM2), is performed via two internal data busses (iBus1, iBus2), where the data to be transmitted per iBurst are identical to the data of a corresponding external data packet (eBurst). For further iBursts, the data transmission is performed exclusively via the first internal data bus. An independent claim is included for a method of transmitting data in a memory system.