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Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias

机译:使用可调偏置在相位内插器中保持时钟边沿的所需斜率的方法和装置

摘要

Methods and apparatus are provided for maintaining a desired slope of clock edges in a phase interpolator using an adjustable bias. The disclosed phase interpolator comprises at least one delay element to generate at least two interpolation signals each having an associated phase and a variable slope unit associated with each of the at least two interpolation signals, wherein a slope of each of the variable slope units is controlled by a bias signal and is varied based on a data rate of the interpolation signals. The slope is varied to maintain a desired slope of clock edges associated with the interpolation signals. The slope can be maintained, for example, between approximately the value of the delay between consecutive clock edges and twice the value of the delay between consecutive clock edges.
机译:提供了用于使用可调偏置来在相位内插器中保持时钟边缘的期望斜率的方法和装置。公开的相位内插器包括至少一个延迟元件,以产生至少两个内插信号,每个内插信号具有相关的相位;以及可变斜率单元,该可变斜率单元与至少两个内插信号的每一个相关联,其中,每个可变斜率单元的斜率被控制。通过偏置信号来改变,并且基于内插信号的数据率来改变。改变斜率以维持与内插信号相关联的时钟边缘的期望斜率。例如,可以将斜率维持在连续时钟边沿之间的延迟值的大约与连续时钟边沿之间的延迟值的两倍之间。

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